1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to an improved ROM code region.
2. Description of Related Art
FIGS. 1A shows a schematic plan view of a prior art ROM device 10. FIG. 1B shows a cross section taken along line 1B--1B in FIG. 1 of the prior art device 10 including a semiconductor substrate 6 coated with a gate oxide layer 7. Referring to FIG. 1A, device 10 includes an array of buried bit lines BL1 and BL2 and with an array of word lines WL1, WL2, and WL3 passing over the tops of the bit lines BL1 and BL2. Referring to FIG. 1A and FIG. 1B, a ROM code implant region 9' is located below an opening 4 in the photoresist mask 5 at the intersection of word line WL2 and the space between bit lines BL1 and BL2.
Upon gate oxide layer 7 is an array of word lines represented by lines WL1, WL2, and WL3 and photoresist mask 5 formed above the word lines WL1, WL2, and WL3 in the process of manufacture during an early stage in which a layer of photoresist 5 has been formed over the device 10 with an opening 4 above the ROM. The section in FIG. 1B shows code implantation 9' of implanted boron ions 9. The section line 1B--1B is taken between the two bit lines BL1 and BL2. The problem with that prior art process is the side diffusion 9" of boron causing lower cell current in "on-cells" adjacent to the implanted cell region 9'.